The present invention relates to a microprocessor and, more particularly, to a microprocessor suitable for being applied to an information processing system equipped with a cache memory unit.
As well known in the art, a cache memory unit is widely employed in an information processing system as one means of enhancing processing, speed and efficiency. However, the cache memory unit fetches all the data responsive to access requests from a microprocessor often resulting in a decrease in the processing efficiency. For example, peripheral I/O (Input/Output) devices are generally initiated in the state controls thereof in response to a data access bus cycle by the microprocessor. Hence, the data, which are read from or written into the peripheral I/O devices responsive to IN/OUT instructions, are not required to be fetched in the cache memory unit. If those data are fetched in the cache memory unit, however, some important data, which have already been stored in the cache memory unit, disappear therefrom. As another example, in the execution of STRING instructions, in which a string of data are transferred between the I/O device and a main memory or between two storage areas of the main memory, if the cache memory unit having small memory capacity is employed, it would be filled with the string of data thus transferred, so that the effective and important data also disappear therefrom.
Therefore, such data are required to bypass the cache memory unit without being fetched therein. For this purpose, the cache memory unit is constructed to have a cache bypass control terminal and to inhibit a data caching operation in the data access bus cycle when an active level is applied to the cache bypass control terminal.
The microprocessor produces a set of bus status signals simultaneously with the initiation of the data access bus cycle. The set of bus status, signals represents the kind of the data accesses. Accordingly, the level or signal to be applied to the cache bypass control terminal of the cache memory unit can be controlled by decoding the set of bus status signals.
However, the kinds of information represented by the bus status, signals are restricted. For this reason, a fine cache bypass control fitting to a recent information processing system employing a high performance microprocessor cannot be attained. In particular, a memory read access for setting a certain value into a privilege register in PRIVILEGE instructions and a task context data access in TASK SWITCHING instructions are not distinguished from the access bus cycles in normal instructions, such as a move instruction and an operation instruction by the content of the bus status signals. As a result, the privilege data and the task context data are fetched or stored in the cache memory unit, although the access frequency to such data is low.